1. Field of the Invention
The present invention relates to a chip package structure and fabricating method thereof. More particularly, the present invention relates to a flip chip bonded chip package structure and process for fabricating the same.
2. Description of the Related Art
As the need for communication is increasingly important in our society, the market for various types of electronic devices expands rapidly. To prepare for the upcoming trend, chip packages often have a design that reflects our need for a digital network connection and more personalized electronic equipment. One way of meeting our demands is to produce highly integrated digital devices having higher processing speed and more powerful functions, a lighter body and yet cheaper to produce. In other words, chip packages continue to improve through miniaturization and increasing its packing density. In the flip chip bonding technique of fabricating chip packages, bumps are used to connect a chip with a carrier. Since the flip chip bonding technique has a much shorter wiring length relative to a conventional wire bonded package, signal transmission between the chip and the carrier is significantly increased. As a result, flip chip packages have gradually become one of the most widely adopted high-density package products.
FIG. 1 is a schematic cross-sectional view of a conventional flip chip package. As shown in FIG. 1, the chip package 40 comprises a chip 50 having an active surface 52, a carrier 80 and a plurality of bumps 60. The active surface 52 has a plurality of bonding pads 54 thereon. The surface of the carrier 80 has a plurality of contacts 84. The bumps 60 are disposed on the bonding pads 54 of the chip 50. The chip 50 and the carrier 80 are electrically connected through the bonding pads 54, the bumps 60 and the contacts 84 on the carrier 80.
To protect the chip 50 against damage due to the infiltration of moisture and the bumps 60 linking the chip 50 and the carrier 80 against physical damage due to mechanical stress, an underfill layer 70 often fills the gap between the chip 50 and the carrier 80. However, due to the difference in coefficient of thermal expansion (CTE) between the chip 50, the bumps 60, the underfill layer 70 and the carrier 80, the chip package 40 is vulnerable to thermal stress failure resulting from cyclic temperature variations due to repeated operation.
In general, the thermal stress induced by a difference in coefficient of thermal expansion is frequently concentrated in areas close to the junction between the bump and the carrier. Since cyclic stress in these areas can cause fatigue, cracks may propagate inside the bumps. Ultimately, the reliability of the electrical connection between the chip and the carrier will be compromised. One way to resolve this problem is to increase the area of contact between the bump and the contact and reduce thermal stress concentration. Yet, increasing the contact area must be accompanied by a corresponding increase in the pitch separating adjacent contacts to reduce the probability of having an abnormal electrical connection between the neighboring bumps. The prevention of abnormal connection between neighboring bumps also limits the number of contacts that can be disposed between a given chip and carrier. Furthermore, increasing the area of contact between the bumps and the contacts will lower the average height of the bumps and subject the bumps to a higher thermal stress.
In brief, a high priority is placed on finding a method capable of reducing as much damage to the bumps as possible due to a difference in the coefficient of thermal expansion between the chip, the bumps, the underfill layer and the carrier of a chip package.